v2 prototypeHEADv2-workingmaster

NOTE: the simulations aren't working atm

1 files changed, 11 insertions, 9 deletions

diff --git a/newnewexi.pld b/newnewexi.pld
index 5f58bec..a229117 100644
--- a/newnewexi.pld
+++ b/newnewexi.pld
@@ -21,23 +21,25 @@ Device     F1504ISPTQFP44;
 /** EXI-side pins  **/

 

 Pin 37 = EXI_CLK;	/*  IN: EXI bit clock (act on rising edge) */

-Pin 34 = !EXI_CS;	/*  IN: EXI chip select (active-low) - device in standby when FALSE */

+Pin 38 = !EXI_CS;	/*  IN: EXI chip select (active-low) - device in standby when FALSE */

 Pin 43 = EXI_DI;	/* OUT: EXI data (slave out) */

 Pin 42 = EXI_DO;	/*  IN: EXI data (slave in) */

 Pin 44 = EXI_INT;	/* OUT: EXI interrupt (not used) */

 

 /** USB-side pins  **/

 

-/* P22: 4, P21: 2, P20: 1, P18: 7, P15: 5, P14: 6, P13: 3, P23: 0 */

-Pin [23, 20, 21, 13, 22, 15, 14, 18] = [FIFO0..7];	/* I/O: USB data lines */

-Pin 27 = !USB_RXF;			/*  IN: USB data in FIFO? */

-Pin 25 = !USB_TXE;			/*  IN: USB can write? */

-Pin 11 = !USB_RD;			/* OUT: USB read request (need RXF TRUE) */

-Pin 12 = USB_WR;			/* OUT: USB write request (need TXE TRUE) */

-Pin 28 = !USB_PWREN;			/*  IN: USB bus ready? */

+/* P33: FIFO0, P32: FIFO4, P31: FIFO2, P30: FIFO1, P28: FIFO7, P27: FIFO5, P26: FIFO6, P25: FIFO3, P23:  */

+/* 0: 34, 4: 33, 2: 31, 1: 30, 7: 28, 5: 27, 6: 25, 3: 23 */

+/* 34, 30, 31, 23, 33, 27, 25, 28 */

+Pin [34, 30, 31, 23, 33, 27, 25, 28] = [FIFO0..7];	/* I/O: USB data lines */

+Pin 10 = !USB_RXF;			/*  IN: USB data in FIFO? */

+Pin 11 = !USB_TXE;			/*  IN: USB can write? */

+Pin 21 = !USB_RD;			/* OUT: USB read request (need RXF TRUE) */

+Pin 22 = USB_WR;			/* OUT: USB write request (need TXE TRUE) */

+Pin 8 = !USB_PWREN;			/*  IN: USB bus ready? */

 

 /** Extra pins **/

-Pin 10 = !LED;	/* OUT: Master-controlled LED */

+Pin 13 = !LED;	/* OUT: Master-controlled LED */

 

 /**   Declarations and Intermediate Variable Definitions  **/