From 5018f53a7f9a7f9a2517c27df9586b973cf73a5f Mon Sep 17 00:00:00 2001 From: bigfoot547 Date: Mon, 27 Apr 2026 00:16:53 -0500 Subject: target bigger CPLD --- Makefile | 6 +++--- newnewexi.pld | 57 +++++++++++++++++++++++++++++++-------------------------- newnewexi.si | 58 +++++++++++++++++++++++++++++++++++++++------------------- 3 files changed, 73 insertions(+), 48 deletions(-) diff --git a/Makefile b/Makefile index 2ef1916..919840a 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ CUPL_INSTALL := C:\WinCUPL CUPL_LIB = ${CUPL_INSTALL}\Shared\cupl.dl CUPL_PATH = ${CUPL_INSTALL}\Shared\cupl.exe -CUPL_DEV := F1502ISPTQFP44 +CUPL_DEV := F1504ISPTQFP44 # SIM config CSIM_PATH = ${CUPL_INSTALL}\Shared\csim.exe @@ -11,7 +11,7 @@ CSIM_PATH = ${CUPL_INSTALL}\Shared\csim.exe # (replace with fitter matching device) FITTER_PATH := ${CUPL_INSTALL}\Fitters\fit1502.exe FIT_PKG := TQFP44 -FIT_TECH := ATF1502ASV +FIT_TECH := ATF1504ASV FIT_ARG = -device ${FIT_PKG} -tech ${FIT_TECH} # bottles config @@ -41,7 +41,7 @@ fit: ${PROJ_NAME}.tt3 sim: ${PROJ_NAME}.so clean: - rm -f *.abs *.lst *.pla *.doc *.fit *.sim *.tt2 *.tt3 + rm -f *.abs *.io *.jed *.pin *.wo *.lst *.pla *.doc *.fit *.sim *.tt2 *.tt3 %.pla: %.pld %.si # Real artifacts: .abs, .lst, .pla, .doc diff --git a/newnewexi.pld b/newnewexi.pld index 0e2bb9d..b5a6d85 100644 --- a/newnewexi.pld +++ b/newnewexi.pld @@ -6,7 +6,7 @@ Designer ; Company ; Assembly ; Location ; -Device F1502ISPTQFP44; +Device F1504ISPTQFP44; /***********************************************************/ /* */ @@ -19,22 +19,22 @@ Device F1502ISPTQFP44; /** EXI-side pins **/ Pin 37 = EXI_CLK; /* IN: EXI bit clock (act on rising edge) */ -Pin 8 = !EXI_CS; /* IN: EXI chip select (active-low) - device in standby when FALSE */ -Pin 10 = EXI_DO; /* OUT: EXI data (slave out) */ -Pin 11 = EXI_DI; /* IN: EXI data (slave in) */ -Pin 12 = EXI_INT; /* OUT: EXI interrupt (not used) */ +Pin 34 = !EXI_CS; /* IN: EXI chip select (active-low) - device in standby when FALSE */ +Pin 42 = EXI_DO; /* OUT: EXI data (slave out) */ +Pin 43 = EXI_DI; /* IN: EXI data (slave in) */ +Pin 44 = EXI_INT; /* OUT: EXI interrupt (not used) */ /** USB-side pins **/ -Pin [35..33, 31, 30, 28, 27, 25] = [FIFO0..7]; /* I/O: USB data lines */ -Pin 23 = !USB_RXF; /* IN: USB data in FIFO? */ -Pin 22 = !USB_TXE; /* IN: USB can write? */ -Pin 21 = !USB_RD; /* OUT: USB read request (need RXF TRUE) */ -Pin 20 = USB_WR; /* OUT: USB write request (need TXE TRUE) */ -Pin 18 = !USB_PWREN; /* IN: USB bus ready? */ +Pin [22..20, 18, 15..12] = [FIFO0..7]; /* I/O: USB data lines */ +Pin 11 = !USB_RXF; /* IN: USB data in FIFO? */ +Pin 10 = !USB_TXE; /* IN: USB can write? */ +Pin 23 = !USB_RD; /* OUT: USB read request (need RXF TRUE) */ +Pin 25 = USB_WR; /* OUT: USB write request (need TXE TRUE) */ +Pin 27 = !USB_PWREN; /* IN: USB bus ready? */ /** Extra pins **/ -Pin 6 = LED; /* OUT: Master-controlled LED */ +Pin 33 = LED; /* OUT: Master-controlled LED */ /** Declarations and Intermediate Variable Definitions **/ @@ -47,7 +47,7 @@ Node MODE_WR; /* EXI write request */ Node MODE_ID; /* EXI identify request */ Node LED_STATE; /* EXI requested LED on? */ Node RESET_MODE; /* Reset since last clock */ -/* Node WRITE_NOW; */ /* Writing USB data now? */ +Node WRITE_NOW; /* Writing USB data now? */ Field USB_Data = [FIFO7..0]; /* USB FIFO data (if USB_RD TRUE) */ Field EXI_Command = [EXI_CMD3..0]; /* EXI command field */ @@ -55,7 +55,7 @@ Field EXI_Command = [EXI_CMD3..0]; /* EXI command field */ Field EXI_State = [EXI_SEQ3..0]; /* Clock state */ Enable = EXI_CS & USB_PWREN; -LED = LED_STATE # !Enable; /* LED should be on if USB isn't set up yet, or if requested by EXI */ +LED = LED_STATE # !USB_PWREN; /* LED should be on if USB isn't set up yet, or if requested by EXI */ $Repeat i = [0..3] /* EXI_SEQ state machine clocked by EXI (assuming we're selected) */ @@ -71,7 +71,7 @@ $Repeat i = [0..7] FIFO{i}.CKMUX = EXI_CLK; FIFO{i}.CE = EXI_State:'h'{11-i} & Enable; FIFO{i}.D = EXI_DI; -FIFO{i}.OE = USB_WR; +FIFO{i}.OE = WRITE_NOW; $RepEnd MODE_RD.CKMUX = EXI_CLK; @@ -80,8 +80,8 @@ MODE_ID.CKMUX = EXI_CLK; MODE_ID.CE = Enable; MODE_WR.CKMUX = EXI_CLK; MODE_WR.CE = Enable; -/* WRITE_NOW.CKMUX = EXI_CLK; */ -/* WRITE_NOW.CE = Enable; */ +WRITE_NOW.CKMUX = EXI_CLK; +WRITE_NOW.CE = Enable; EXI_DO.CKMUX = EXI_CLK; EXI_DO.CE = Enable; @@ -106,24 +106,27 @@ EXI_DO.AR = Reset; MODE_RD.AR = Reset; MODE_ID.AR = Reset; MODE_WR.AR = Reset; -/* WRITE_NOW.AR = Reset; */ +WRITE_NOW.AR = Reset; USB_RD.AR = Reset; USB_WR.AR = Reset; SequenceD EXI_State { - Present 'd'0 Next 'd'1 Out MODE_RD.K Out MODE_ID.K Out MODE_WR.K Out USB_RD.K Out USB_WR.K; + Present 'd'0 Next 'd'1 Out MODE_RD.K Out MODE_ID.K Out MODE_WR.K Out USB_RD.K Out USB_WR.K Out WRITE_NOW.K; Present 'd'1 Next 'd'2; Present 'd'2 Next 'd'3; Present 'd'3 - /* .D is used here because EXI_Command (Q) is not necessarily updated by the time this logic occurs. */ - If EXI_Command:'h'A & USB_RXF Next 'd'4 /* Ready to read */ + /* !EXI_DI term because the low bit of EXI_Command hasn't necessarily been set yet. + * Without that check, B commands are misinterpreted as A commands. */ + If EXI_Command:'h'A & !EXI_DI & USB_RXF Next 'd'4 /* Ready to read */ Out MODE_RD.J /* Enter reading mode. */ Out EXI_DO /* Tell GC. */ Out USB_RD.J /* Trigger USB read */; - If EXI_Command:'h'A & !USB_RXF Next 'd'15 /* Not ready to read. EXI_DO stays low. */; + If EXI_Command:'h'A & !EXI_DI & !USB_RXF Next 'd'15 /* Not ready to read. EXI_DO stays low. */; Default Next 'd'4; Present 'd'4 + If EXI_Command:'h'7 Next 'd'15 Out LED_STATE.K; + If EXI_Command:'h'8 Next 'd'15 Out LED_STATE.J; If EXI_Command:'h'9 Next 'd'5 Out MODE_ID.J Out EXI_DO /* Send bit 7 of ID byte */; If EXI_Command:'h'B & USB_TXE Next 'd'5 /* Ready to write */ Out MODE_WR.J /* Enter writing mode */ @@ -131,8 +134,6 @@ SequenceD EXI_State { If EXI_Command:'h'B & !USB_TXE Next 'd'15; /* Not ready to write. */ If EXI_Command:'h'C & USB_TXE Next 'd'15 Out EXI_DO; If EXI_Command:'h'D & USB_RXF Next 'd'15 Out EXI_DO; - If EXI_Command:'h'7 Next 'd'15 Out LED_STATE.J; - If EXI_Command:'h'8 Next 'd'15 Out LED_STATE.K; Default Next 'd'5; Present 'd'5 /* ID bit 6: 0 */ @@ -162,23 +163,27 @@ SequenceD EXI_State { Present 'd'11 /* ID bit 0: 0 */ If MODE_RD & FIFO3.IO Next 'd'12 Out EXI_DO; + /* B cmd: received last bit of data over EXI. Let's get the FTDI chip ready. */ + If MODE_WR Next 'd'12 Out USB_WR.J; Default Next 'd'12; Present 'd'12 If MODE_RD & FIFO2.IO Next 'd'13 Out EXI_DO; - /* B CMD: Received the data over EXI, let's write it now. */ - If MODE_WR Next 'd'13 Out USB_WR.J; + /* B cmd: Data actually in register. */ + If MODE_WR Next 'd'13 Out WRITE_NOW.J; Default Next 'd'13; Present 'd'13 If MODE_RD & FIFO1.IO Next 'd'14 Out EXI_DO; Default Next 'd'14; Present 'd'14 If MODE_RD & FIFO0.IO Next 'd'15 Out EXI_DO; + /* B cmd: Disable USB_WR here. It must happen strictly before WRITE_NOW is disabled. */ If MODE_WR Next 'd'15 Out USB_WR.K; Default Next 'd'15; Present 'd'15 Next 'd'15 Out USB_RD.K /* Reset all pins */ Out USB_WR.K + Out WRITE_NOW.K Out MODE_RD.K Out MODE_WR.K Out MODE_ID.K; diff --git a/newnewexi.si b/newnewexi.si index 2caaf6a..3e11b77 100644 --- a/newnewexi.si +++ b/newnewexi.si @@ -6,7 +6,7 @@ Designer ; Company ; Assembly ; Location ; -Device F1502ISPTQFP44; +Device F1504ISPTQFP44; BASE: hex; ORDER: EXI_CS, USB_PWREN, %1, Enable, %1, USB_Data, %1, USB_RXF, %1, USB_RD, USB_WR, %3, EXI_CLK, %2, EXI_DI, %2, EXI_Command, %2, EXI_State, %2, MODE_RD, %2, EXI_DO; @@ -38,24 +38,44 @@ $TRACE 1; 0 1 * 11010100 1 * L 0 0 "*" "*" * * 0 1 * 11010100 1 * L 0 0 "*" "*" * * -ORDER: EXI_CLK, %1, EXI_CS, USB_PWREN, %1, USB_Data, %1, USB_RXF, USB_TXE, %1, USB_RD, USB_WR, %3, EXI_DI, %2, EXI_Command, %2, EXI_State, %2, EXI_DO; +ORDER: EXI_CLK, %1, EXI_CS, USB_PWREN, %1, USB_Data, %1, USB_RXF, USB_TXE, %1, USB_RD, USB_WR, %1, WRITE_NOW, %3, EXI_DI, %2, EXI_Command, %2, MODE_WR, %1, EXI_State, %2, EXI_DO; VECTORS: $TRACE 0; -0 0 0 "*" 1 X L * X **** **** * -0 1 1 "*" 1 0 L * X LLLL **** * -C 1 1 "*" 1 0 L * 1 HLLL **** * -C 1 1 "*" 1 1 L * 0 HLLL **** * -C 1 1 "*" 1 1 L * 1 HLHL **** * -C 1 1 "*" 1 1 L * 1 HLHH **** * -C 1 1 "*" 1 1 L * 1 HLHH **** * -C 1 1 "*" 1 1 L * 0 HLHH **** * -C 1 1 "*" 1 1 L * 1 HLHH **** * -C 1 1 "*" 1 1 L * 0 HLHH **** * -C 1 1 "*" 1 1 L * 0 HLHH **** * -C 1 1 "*" 1 1 L * 1 HLHH **** * -C 1 1 "*" 1 1 L * 1 HLHH **** * -C 1 1 "*" 1 1 L * 1 HLHH **** * -C 1 1 "*" 1 1 L * 0 HLHH **** * -C 1 1 "*" 1 1 L * 0 HLHH **** * -C 1 1 "*" 1 1 L * 0 HLHH **** * +0 0 0 "*" 1 X L * * X **** * **** * +0 1 1 "*" 1 0 L * * X LLLL * **** * +C 1 1 "*" 1 0 L * * 1 HLLL * **** * +C 1 1 "*" 1 1 L * * 0 HLLL * **** * +C 1 1 "*" 1 1 L * * 1 HLHL * **** * +C 1 1 "*" 1 1 L * * 1 HLHH * **** * +C 1 1 "*" 1 1 L * * 1 HLHH * **** * +C 1 1 "*" 1 1 L * * 0 HLHH * **** * +C 1 1 "*" 1 1 L * * 1 HLHH * **** * +C 1 1 "*" 1 1 L * * 0 HLHH * **** * +C 1 1 "*" 1 1 L * * 0 HLHH * **** * +C 1 1 "*" 1 1 L * * 1 HLHH * **** * +C 1 1 "*" 1 1 L * * 1 HLHH * **** * +C 1 1 "*" 1 1 L * * 1 HLHH * **** * +C 1 1 "*" 1 1 L * * 0 HLHH * **** * +C 1 1 "*" 1 1 L * * 0 HLHH * **** * +C 1 1 "*" 1 1 L * * 0 HLHH * **** * +C 1 1 "*" 1 1 L * * 0 HLHH * **** * + +ORDER: EXI_CLK, %1, EXI_CS, USB_PWREN, %1, EXI_DI, %2, EXI_Command, %2, LED_STATE, LED, %1, EXI_DO; + +VECTORS: +0 0 0 X **** L H L +0 1 1 X **** L L L +C 1 1 1 **** L L L +C 1 1 0 **** L L L +C 1 1 0 **** L L L +C 1 1 0 **** L L L +C 1 1 0 **** H H L +0 0 1 X **** H H L +C 1 1 0 **** H H L +C 1 1 1 **** H H L +C 1 1 1 **** H H L +C 1 1 1 **** H H L +C 1 1 0 **** L L L +C 0 1 X **** L L L +0 0 0 X **** L H L -- cgit v1.2.3-70-g09d2