From fff75f489768a8f87157199cad6905339b333ccb Mon Sep 17 00:00:00 2001 From: bigfoot547 Date: Fri, 1 May 2026 16:42:06 -0500 Subject: modify pin assignments to make routing easier --- newnewexi.pld | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/newnewexi.pld b/newnewexi.pld index d8d9e50..de65a86 100644 --- a/newnewexi.pld +++ b/newnewexi.pld @@ -22,18 +22,19 @@ Device F1504ISPTQFP44; Pin 37 = EXI_CLK; /* IN: EXI bit clock (act on rising edge) */ Pin 34 = !EXI_CS; /* IN: EXI chip select (active-low) - device in standby when FALSE */ -Pin 42 = EXI_DO; /* OUT: EXI data (slave out) */ -Pin 43 = EXI_DI; /* IN: EXI data (slave in) */ +Pin 43 = EXI_DO; /* OUT: EXI data (slave out) */ +Pin 42 = EXI_DI; /* IN: EXI data (slave in) */ Pin 44 = EXI_INT; /* OUT: EXI interrupt (not used) */ /** USB-side pins **/ -Pin [22..20, 18, 15..12] = [FIFO0..7]; /* I/O: USB data lines */ -Pin 11 = !USB_RXF; /* IN: USB data in FIFO? */ -Pin 10 = !USB_TXE; /* IN: USB can write? */ -Pin 23 = !USB_RD; /* OUT: USB read request (need RXF TRUE) */ -Pin 25 = USB_WR; /* OUT: USB write request (need TXE TRUE) */ -Pin 27 = !USB_PWREN; /* IN: USB bus ready? */ +/* P22: 4, P21: 2, P20: 1, P18: 7, P15: 5, P14: 6, P13: 3, P23: 0 */ +Pin [23, 20, 21, 13, 22, 15, 14, 18] = [FIFO0..7]; /* I/O: USB data lines */ +Pin 27 = !USB_RXF; /* IN: USB data in FIFO? */ +Pin 25 = !USB_TXE; /* IN: USB can write? */ +Pin 12 = !USB_RD; /* OUT: USB read request (need RXF TRUE) */ +Pin 11 = USB_WR; /* OUT: USB write request (need TXE TRUE) */ +Pin 28 = !USB_PWREN; /* IN: USB bus ready? */ /** Extra pins **/ Pin 33 = !LED; /* OUT: Master-controlled LED */ -- cgit v1.2.3-70-g09d2